1. Field of the Invention
The present invention relates generally to semiconductor fabrication, and more particularly, to systems and methods for vertically integrating semiconductor devices.
2. Description of Related Art
Vertical integration of semiconductor devices, commonly referred to as “3D interconnect,” may be accomplished using die-to-wafer or wafer-to-wafer flows by which a “donor” die or wafer is stacked on top of a “host” wafer. Of these two methods, die-to-wafer processes provide the most advantageous form of integration. For example, die-to-wafer processes includes the ability to pre-screen or otherwise test donor die, thus allowing the manufacturer to select only devices that have passed the test for further integration and discard the bad ones. In contrast, in a wafer-to-wafer process, all die (good and bad) present on the donor wafer are integrated into the host wafer (which also contains good and bad die).
Additionally, the die-to-wafer process can maximize the number of donor die that are fabricated on a wafer when the donor die are smaller than the host die. For example, if donor die are smaller than host die, the donor wafer can have the donor die close together so as to maximize donor wafer yield. Meanwhile, wafer-to-wafer integration typically results in unused silicon between the individual donor die.
Despite the foregoing, there are several significant drawbacks with respect to existing die-to-wafer integration methods. For example, die-to-wafer integration generally requires that die be individually aligned and bonded to the host wafer. This step can be very time consuming, and it may take many hours per wafer depending upon the required alignment accuracy, die bond time, and the number of dies per wafer. Additionally, die-to-wafer processes produce a non-planar surface that is incompatible with certain 3D integrations requiring further wafer-level processing.